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Institute Mihailo Pupin
Institute Mihailo Pupin is the leading Serbian R&D institution in the field of Information & Communication Techologies.

Automation & Control Systems Ltd
The Automation & Control Systems Ltd is the core division of the Institute Mihailo Pupin, and the owner of the projects: ATLAS Systems and ATLAS-MAX.

References
The long list of the Institute's references and customers is the best proof of its high professional and techological achievments.

VIEW SCADA & DCS
The other related IMP project: VIEW4 Software Package for control of complex processes

You are here:     piko-ATLAS System p-Organization Hardware p-Organization I2C Distribution Rail
I2C TBUS Distribution Strip/Rail

 

Inter-Integrated Circuit Bus (also identified as: Inter-IC or I2C Bus) is a multi-master serial single-ended computer bus invented by Philips that is used to attach peripherals to a motherboard, embedded system, or cellphone.  I2C uses only two bidirectional open-drain lines, Serial Data Line - SDA and Serial Clock - SCL, pulled up with resistors.  The I2C bus has two roles for nodes:

  • Master node - node that issues the clock and addresses slaves (multiple master nodes could be applied);
  • Slave node - node that receives the clock line and address.

Here is an example with one master node (a microcontroller mC) and three slave nodes (an ADC, a DAC, and another microcontroller mC):

I2C Example

Typical Vdd voltages are +5V or +3.3V (although systems with other voltages are permitted).  The I2C reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus.

The master is initially in master transmit mode by sending a START bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to, or read(1) from the slave.  If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively).  The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high.

A physical implementation of the I2C Bus was provided via a special distribution strip, which consists of a metal rail with a certain number of pluggable Phoenix TBUS edge connectors for individual pATLAS module insertions, as presented here (w/o and with plugged modules):

I2C TBUS Distribution Strip

Modules on I2C TBUS Rail

 

I2C Bus is an extremely simple serial bus that includes only five lines:

  1. GND Ground
  2. RST Reset
  3. SCL System Clock
  4. SDA System Data
  5. VDD Power Supply +12VDC

The I2C communication is managed by the master CPU module, which scans all participating I/O modules in accordance with the actual system configuration.  Each slave I/O module is identified by a single (or multiple) I2C address, and replies to the CPU query.  The implemented query/reply timing guaranties a bidirectional communication with all digital input modules within 1ms time frame, enabling a proper 1ms chronological event recording (whenever needed).  Communication with other I/O modules depends on the actual system I/O capacity and input/output signal types, but always stays within the real-time range.

For the best system performance, the I2C bus is terminated by a special active I2C termination module, which also includes power supply LED indicator:

I2C Termination ModuleI2C Termination PCB

 

System reset is provided via RST line, and could be software or hardware generated.  A hardware reset is invoked via a special front-panel push-button on the CPU module.